1. Field of the Invention
The present invention relates to an I/O circuit placement method and semiconductor device using the same.
2. Description of the Related Art
FIG. 1 shows a conventional semiconductor chip having application specific integrated circuits (ASIC). Input/Output buffer circuits 12 (hereinafter referred as I/O circuits) are arranged at the periphery of the chip 10. As shown in FIG. 1, each side of the semiconductor chip 10 has one row of I/O circuits, and the four rows of I/O circuits form a loop.
Conventionally, the I/O circuits in a semiconductor chip are always arranged in one loop around the core circuit 14. Thus, a large number of I/O circuits 12 at the periphery of the chip may enlarge the area of the semiconductor chip 10, and is referred to as the pad limit design. To address this problem, conventional methods have attempted with difficulty to narrow the size of the I/O circuits.